Technology Mapping with Boolean Matching, Supergates and Choices

As an important step of any design flow, technology mapping, expresses logic functions of a netlist using gates from a technology library, in the presence of various design constraints. This paper proposes a new approach to technology mapping, which relies and enhances upon several known techniques, integrated and fine tuned to work in a new way. The previous work on DAG mapping is extended, by proposing new methods for enumerating mapping choices and performing Boolean matching, which guarantees delay-optimum phase assignment at the gate boundaries. Two ways of capturing flexibility in technology mapping are explored and compared: supergates and choice nodes. An implementation based on these ideas significantly outperforms state-of-the-art mappers in terms of delay, area and run-time on academic and industrial benchmarks.